Application Note 86 January 2001 A Standards Lab Grade 20-Bit DAC with 0.1ppm/C Drift The Dedicated Art of Digitizing One Part Per Million Jim Williams J. Brubaker P. Copley J. Guerrero F. Oprescu INTRODUCTION Significant progress in high precision, instrumentation grade D-to-A conversion has recently occurred. Ten years ago 12-bit D-to-A converters (DACs) were considered premium devices. Today, 16-bit DACs are available and increasingly common in system design. These are true precision devices with less than 1LSB linearity error and 1ppm/C drift.1 Nonetheless, there are DAC applications that require even higher performance. Automatic test equipment, instruments, calibration apparatus, laser trimmers, medical electronics and other applications often require DAC accuracy beyond 16 bits. 18-bit DACs have been produced in circuit assembly form, although they are expensive and require frequent calibration. 20 and even 23+ (0.1ppm!) bit DACs are represented by manually switched Kelvin-Varley dividers. These devices, although amazingly accurate, are large, slow and extremely costly. Their use is normally restricted to standards labs.2 A useful development would be a practical, 20-bit (1ppm) DAC that is easily constructed and does not require frequent calibration. differences the user input word with the LTC2400 output, presenting a corrected code to the slave DAC. In this fashion, the slave DAC's drifts and nonlinearity are continuously corrected by the loop to an accuracy determined by the A-to-D converter and VREF4. The sole DAC requirement is that it be monotonic. No other components in the loop need to be stable. VREF 20-BIT USER INPUT CODE DIGITAL CODE COMPARATOR FEEDBACK CODE LTC2400 "MASTER" A-TO-D VIN 20-BIT (1PPM) ANALOG OUTPUT CORRECTED CODE 20-BIT "SLAVE" DAC VOUT AN86 F01 Figure 1. Conceptual Loop-Based 20-Bit DAC. Digital Comparison Allows A-to-D to Correct DAC Errors. LTC2400 A-to-D's Low Uncertainty Characteristics Permit 1ppm Output Accuracy , LTC and LT are registered trademarks of Linear Technology Corporation. 20-Bit DAC Architecture Figure 1 diagrams the architecture of a 20-bit (1ppm) DAC. This scheme is based on the availability of a true 1ppm analog-to-digital converter with scale and zero drifts below 0.02ppm/C. This device, the LTC(R)2400, is used as a feedback element in a digitally corrected loop to realize a 20-bit DAC.3 In practice, the "slave" 20-bit DAC's output is monitored by the "master" LTC2400 A-to-D, which feeds digital information to a code comparator. The code comparator Note 1: See Appendix A, "A History of High Accuracy Digital-to-Analog Conversion," for a review of high accuracy digital-to-analog conversion. Note 2: Consult Appendix C, "Verifying Data Converter Linearity to 1ppm," for discussion on Kelvin-Varley dividers. Also, see Appendix A, "A History of High Accuracy Digital-to-Analog Conversion." Note 3: The LTC2400 analog-to-digital converter is profiled in Appendix B, "The LTC2400--A Monolithic 24-Bit Analog-to-Digital Converter." Note 4: D-to-A converters have been placed in loops to make A-to-D converters for a long time. Here, an A-to-D converter feeds back a loop to form a D-to-A converter. There seems a certain justified symmetry to this development. Turnabout is indeed fair play. AN86-1 Application Note 86 This loop has a number of desireable attributes. As mentioned, accuracy limitations are set by the A-to-D converter and its reference. No other components need be stable. Additionally, loop behavior averages low order bit indexing and jitter, obviating the loop's inherent smallsignal instability. Finally, classical remote sensing may be used or digitally based sensing is possible by placing the A-to-D converter at the load. The A-to-D's SO-8 package and lack of external components makes this digitally incarnated Kelvin sensing scheme practical.5 DACs' resultant 24-bit resolution provides 4 bits of indexing range below the 20th bit, ensuring a stable LSB of 1ppm of scale. A1 and A2 transform the DAC's output currents into voltages, which are summed at A3. A3's scaling is arranged so that the correction loop can always capture and correct any combination of zero- and fullscale errors. A3's output, the circuit output, feeds the LTC2400 A-to-D. The LT(R)1010 provides buffering to drive loads and cables. The A-to-D's digital output is differenced against the input word by the code comparator, which produces a corrected code. This corrected code is applied to the MSB and LSB DACs, closing a feedback loop.6 The loop's integrity is determined by A-to-D converter and voltage reference errors.7 The resistor and diodes at the 5V powered A-to-D protect it from inadvertent A3 outputs (power up, transient, lost supply, etc.). A4 is a reference inverter and A5 provides a clean ground potential to both DACs. Circuitry Details Figure 2 is a detailed schematic of the 1ppm DAC. The slave DAC is comprised of two DACs. The upper 16 bits of the code comparator's output are fed to a 16-bit DAC ("MSB DAC"), while the lower bits are converted by a separate DAC ("LSB DAC"). Although a total of 32 bits are presented to the two DACs, there are 8 bits of overlap, assuring loop capture under all conditions. The composite 5V 20-BIT USER INPUT CODE COMMAND INPUTS FROM CODE COMPARATOR 24-BIT FEEDBACK CODE CODE COMPARATOR (SEE APPENDIX D FOR DETAILS) LTC2400 A-TO-D REF IN CS 5V 1N5817 1k 1N5817 + CORRECTED CODE OUT-- 24-BIT WORD DATA INPUTS SERIAL DIGITAL OUT 5VREF (SEE APPENDIX I FOR OPTIONS) A4 LT1001 - 5VREF R LD WR 100pF MSB DAC REF ROS RFS FB R 100pF - IOUT LTC1599 ML BYTE CLVL CLR A1 LT1001 I- OUTPUT AMPLIFIER + 5V 15V 2k* - * = 1% METAL FILM A5 LT1001 A3 LT1001 + DATA INPUTS 5V ML BYTE LD WR CLVL REF + LT1010 OUTPUT - RFB 4.12M* LSB DAC -15V 0.1F 2k* 100pF LTC1599 ROS CLR VREF IOUT I- - 4.12M* A2 LT1001 + AN86 F02 5V Figure 2. Detail of 1ppm DAC. Composite DAC Is Comprised of Two DAC Values Summed at Output Amplifier. LTC2400 A-to-D and Code Comparator Furnish Stabilizing Feedback Note 5: One wonders what Lord Kelvin's response would be to the digizatation of his progeny. Such uncertainties are the residue of progress. Note 6: The code comparator is detailed in Appendix D, "A Processor Based Code Comparator." AN86-2 Note 7: Voltage reference options are discussed in Appendix I, "Voltage References." For tutorial on the LTC2400, refer to Appendix B. Application Note 86 Linearity Considerations Dynamic Performance A-to-D linearity determines overall DAC linearity. The A-to-D has about 2ppm nonlinearity. In applications where this error is permissible, it may be ignored. If 1ppm linearity is required, it is obtainable by correcting the residual linearity error with software techniques. Details on LTC2400 linearity and this feature are presented in Appendices D and E. The A-to-D's conversion rate combines with the loop's sampled data characteristic and slow amplifiers to dictate relatively slow DAC response. Figure 5's slew response requires about 150 microseconds. DC Performance Characteristics Figure 3 is a plot of linearity vs output code. The data shows linearity is within 1ppm over all codes.8 Output noise, measured in a 0.1Hz to 10Hz bandpass, is seen in Figure 4 to be about 0.2LSB.9 This measurement is somewhat corrupted by equipment limitations, which set a noise floor of about 0.2V. Figure 6 shows full-scale DAC settling time to within 1ppm (5V) requires about 1400 milliseconds. A smaller step (Figure 7) of 500V needs only 100 milliseconds to settle within 1ppm.10 Conclusion Summarized 1ppm DAC specifications appear in Figure 9. These specifications should be considered guidelines, as the options and variations noted will affect performance. Consult the appropriate appendices for design specifics and trade-offs. 1.0 0.5 0 SHADED REGION DELINEATES MEASUREMENT UNCERTAINTY DUE TO DAC OUPUT NOISE AND INSTRUMENTATION LIMITATIONS -0.5 -1.0 0 262,144 524,288 786,432 DIGITAL INPUT CODE 500nV/DIV LINEARITY ERROR (ppm) INDICATED MEASUREMENT RESULTS 1,048,576 AN86 F03 Figure 3. Linearity Plot Shows No Error Outside 1ppm for All Codes 2s/DIV AN86 F04.tif Figure 4. Output Noise Indicates Less Than 1V, About 0.2LSB. Measurement Noise Floor, Due to Equipment Limitations, Is 0.2V Note 8: Establishing and maintaining confidence in a 1ppm linearity measurement is uncomfortably close to the state of the art. The technique used is shown in Appendix C, "Verifying Data Converter Linearity to 1ppm." Note 9: Noise measurement considerations appear in Appendix H, "Microvolt Level Noise Measurement." Note 10: Measuring DAC settling time to 1ppm is by no means straightforward, even at the relatively slow speed involved here. See Appendix G, "Measuring DAC Settling Time." AN86-3 1V/DIV 5V/DIV Application Note 86 50s/DIV 5V/DIV Figure 5. DAC Output Full-Scale Slew Characteristics 50ms/DIV 500ms/DIV AN86 F05.tif AN86 F07.tif Figure 7. Small Step Settling Time Measures 100 Milliseconds to Within 1ppm (5V) for a 500V Transition AN86 F06.tif Figure 6. High Resolution Settling Detail After a Full-Scale Step. Settling Time Is 1400 Milliseconds to Within 1ppm (5V) PARAMETER SPECIFICATION Resolution 1ppm Full-Scale Error 4ppm of VREF (Trimmable to 1ppm by VREF Adjustment) Full-Scale Error Drift 0.04ppm/C Exclusive of Reference (0.1ppm/C with LTZ1000A Reference1) Offset Error 0.5ppm Offset Error Drift 0.01ppm/C Nonlinearity 2ppm, Trimmable to Less Than 1ppm2 Output Noise 0.2ppm ( 0.9V, 0.1Hz to 10Hz BW) Slew Rate 0.033V/s Settling Time--Full-Scale Step 1400 Milliseconds Settling Time--500V Step 100 Milliseconds Output Voltage Range 0V to 5V. For Other Ranges See Note 3 Note 1: See Appendix I Note 2: See Appendix E Note 3: See Appendices E and F Figure 8. Summarized Specifications for the 20-Bit DAC Note: This Application Note was derived from a manuscript originally prepared for publication in EDN magazine. AN86-4 Application Note 86 REFERENCES 1. Linear Technology Corporation, "LTC2400 Data Sheet," Linear Technology Corporation, January 1999. 2. Linear Technology Corporation, "LTC2410 Data Sheet," Linear Technology Corporation, April 2000. 3. Keithley Instruments, "Low Level Measurements," Keithley Instruments, 1984. 4. Williams, J., "Testing Linearity of the LTC2400 24-Bit A/D Converter," Linear Technology Corporation, Design Solution 11, November 1999. 5. Seebeck, T. Dr., "Magnetische Polarisation der Metalle und Erze durch Temperatur-Differenz," Abhaandlungen der Preussischen Akademic der Wissenschaften (1822-1823), pp. 265-373. 6. Williams, J., "Component and Measurement Advances Ensure 16-Bit DAC Settling Time," Linear Technology Corporation, Application Note 74, July 1998. 7. Lee, M., "Understanding and Applying Voltage References," Linear Technology Corporation, Application Note 82, November 1999. 8. Williams, J., "Applications Considerations and Circuits for a New Chopper-Stabilized Op Amp," Linear Technology Corporation, Application Note 9, August 1987. 9. Huffman, B., "Voltage Reference Circuit Collection," Linear Technology Corporation, Application Note 42, June 1991. 10. Spreadbury, P. J., "The Ultra-Zener--A Portable Replacement for the Weston Cell?" IEEE Transactions on Instrumentation and Measurement, Vol. 40, No. 2, April 1991, pp. 343-346. 11. Williams, J., "Thermocouple Measurement," Linear Technology Corporation, Application Note 28, February 1988. 12. Hueckel, J. H., "Input Connection Practices for Differential Amplifiers," Neff Inst. Corporation, Duarte, California. 13. Gould Inc., "Elimination of Noise in Low Level Circuits," Gould Inc., Instrument Systems Division, Cleveland, Ohio. 14. Williams, J., "Prevent Low Level Amplifier Problems," Electronic Design, February 15, 1975, p. 62. 15. Pascoe, G., "The Choice of Solders for High Gain Devices," New Electronics (Great Britain), February 6, 1977. 16. Pascoe, G., "The Thermo-E.M.F. of Tin-Lead Alloys," Journal Phys. E, December 1976. 17. Brokaw, A. P., "Designing Sensitive Circuits? Don't Take Grounds for Granted," EDN, October 5, 1975, p. 44. 18. Morrison, R., "Noise and Other Interfering Signals," John Wiley and Sons, 1992. 19. Morrison, R., "Grounding and Shielding Techniques in Instrumentation," Wiley-Interscience, 1986. 20. Vishay Inc., "Vishay Foil Resistors," Vishay Inc., 1999. AN86-5 Application Note 86 APPENDIX A A HISTORY OF HIGH ACCURACY DIGITAL-TO-ANALOG CONVERSION People have been converting digital-to-analog quantities for a long time. Probably among the earliest uses was the summing of calibrated weights (Figure A1, left center) in weighing applications. Early electrical digital-to-analog conversion inevitably involved switches and resistors of different values, usually arranged in decades. The application was often the calibrated balancing of a bridge or reading, via null detection, some unknown voltage. The most accurate resistor-based DAC of this type is Lord Kelvin's Kelvin-Varley divider (Figure, large box). Based on switched resistor ratios, it can achieve ratio accuracies of 0.1ppm (23+ bits) and is still widely employed in standards laboratories.1 High speed digital-to-analog conversion resorts to electronically switching the resistor network. Early electronic DACs were built at the board level using discrete precision resistors and germanium transistors (Figure, center foreground, is a 12-bit DAC from a Minuteman missile D-17B inertial navigation system, circa 1962). The first electronically switched DACs available as standard product were probably those produced by Pastoriza Electronics in the mid 1960s. Other manufacturers followed and discrete- and monolithically-based modular DACs (Figure, right and left) became popular by the 1970s. The units were often potted (Figure, left) for ruggedness, performance or to (hopefully) preserve proprietary knowledge. Hybrid technology produced smaller package size (Figure, left foreground). The development of Si-Chrome resistors permitted precision monolithic DACs such as the LTC1595 (Figure, immediate foreground). In keeping with all things monolithic, the cost-performance trade off of modern high resolution IC DACs is a bargain. Think of it! A 16-bit DAC in an 8-pin IC package. What Lord Kelvin would have given for a credit card and LTC's phone number. Note 1: See Appendix C, "Verifying Data Converter Linearity to 1ppm," for details on Kelvin-Varley Dividers. AN86 FA01.tif Figure A1. Historically Significant Digital-to-Analog Converters Include: Weight Set (Center Left), 23+ Bit Kelvin-Varley Divider (Large Box), Hybrid, Board and Modular Types, and the LTC1595 IC (Foreground). Where Will It All End? AN86-6 Application Note 86 APPENDIX B THE LTC2400--A MONOLITHIC 24-BIT ANALOG-TO-DIGITAL CONVERTER The LTC2400 is a micropower 24-bit A-to-D converter with an integrated oscillator, 4ppm nonlinearity and 0.3ppm RMS noise. It uses delta-sigma technology to provide extremely high stability. The device can be configured for better than 110dB rejection at 50Hz or 60Hz 2%, or it can be driven by an external oscillator for a user defined rejection frequency in the range 1Hz to 120Hz. PARAMETER This ultraprecision A-to-D converter in an SO-8 pin package forms the heart of the 20-bit DAC described in the text. It is significant that the device is used here as a circuit component rather than in the traditional standalone role accorded precision A-to-D converters. This freedom, in keeping with the IC's economy and ease of use, is a noteworthy opportunity. Alert designers will recognize this development and capitalize on it. Key specifications for the A-to-D are given in Figure B1. CONDITIONS Resolution (No Missing Codes) 0.1V VREF VCC 24 Bits Integral Nonlinearity VREF = 2.5V VREF = 5V Offset Error 2.5V VREF VCC 0.5ppm of VREF Offset Error Drift 2.5V VREF VCC 0.01ppm of VREF/C Full-Scale Error 2.5V VREF VCC 4ppm of VREF Full-Scale Error Drift 2.5V VREF VCC 0.02ppm of VREF/C Total Unadjusted Error VREF = 2.5V VREF = 5V Output Noise 2ppm of VREF 4ppm of VREF 5ppm of VREF 1ppm of VREF 1.5VRMS Normal Mode Rejection 60Hz 2% 110dB (Min) Normal Mode Rejection 50Hz 2 110dB (Min) Input Voltage Range 0.125V * VREF to 1.125V * VREF Reference Voltage Range 0.1V VREF VCC Supply Voltage 2.7V VCC 5.5V Supply Current Conversion Mode Sleep Mode CS = 0V CS = VCC 200A 20A Figure B1. Key Specifications for LTC2400 A-to-D Converter. High Linearity and Extreme Stability Allow Realization of 1ppm DAC AN86-7 Application Note 86 APPENDIX C VERIFYING DATA CONVERTER LINEARITY TO 1PPM Help from the Nineteenth Century 10k INTRODUCTION 2k 400 80 INPUT Verifying 1ppm linearity of the DAC and the analog-todigital converter used to construct it requires special considerations. Testing necessitates some form of voltage source that produces equal amplitude output steps for incremental digital inputs. Additionally, for measurement confidence, it is desirable that the source be substantially more linear than the 1ppm requirement. This is, of course, a stringent demand and painfully close to the state of the art. 80 The most linear "D to A" converter is also one of the oldest. Lord Kelvin's Kelvin-Varley divider (KVD), in its most developed form, is linear to 0.1ppm. This manually switched device features ten million individual dial settings arranged in seven decades. It may be thought of as a 3-terminal potentiometer with fixed "end-to-end" resistance and a 7-decade switched wiper position (Figure C1). R = 100k SEVEN-DECADE SWITCHED WIPER POSITION PERMITS SETTING TO 0.1ppm LINEARITY AN86 FC01 OUT 80 COMMON AN86 FC02 Figure C2. A 4-Decade Kelvin-Varley Divider. Additional Decades Are Implemented By Opening Last Switch, Deleting Two Associated 80 Values and Continuing / 5 Resistor Chains Figure C1. Conceptual Kelvin-Varley Divider The actual construction of a 0.1ppm KVD is more artistry and witchcraft than science. The market is relatively small, the number of vendors few and resultant price high. If $13,000 for a bunch of switches and resistors seems offensive, try building and certifying your own KVD. Figure C2 shows a detailed schematic. The KVD shown has a 100k input impedance. A consequence of this is that wiper output resistance is high and varies with setting. As such, a very low bias current follower is required to unload the KVD without introducing significant error. Now, our KVD looks like Figure C3. The LT1010 output buffer allows driving cables and loads and, more subtly, maintains the amplifier's high open-loop gain. AN86-8 10k 0.1F EINPUT - LTC1152 KVD LT1010 OUTPUT + KVD = ELECTRO SCIENTIFIC INDUSTRIES RV-722, FLUKE 720A OR JULIE RESEARCH LABS VDR-307 AN86 FC03 Figure C3. KVD with Buffer Gives Output Drive Capability Application Note 86 Approach and Error Considerations This schematic is deceptively simple. In practice, construction details are crucial. Parasitic thermocouples (Seebeck effect), layout, grounding, shielding, guarding, cable choice and other issues affect achievable performance.1 In fact, as good as the chopper-stabilized LTC1152 is with respect to drift, offset, bias current and CMRR, selection is required if we seek sub-ppm nonlinearity performance. Figure C4, an error budget analysis, details some of the selection criteria. 10k 0.1F - 5V KVD RIN = 100k 30k WORST-CASE OUTPUT RESISTANCE LTC1152 OUTPUT LT1010 + ERROR SOURCE WORST-CASE SPEC REALISTIC SELECTION TARGET ERROR IN PPM EOS 5V 0.5V 0.1 EOST 0.05V/C 0.05V/C 0.01/C IB 50pA 10pA 0.1 CMRR 110dB 140dB 0.1 FINITE GAIN 140dB 140dB 0.1 AN86 FC04 Figure C4. Error Budget Analysis for the KVD Buffer. Selection Permits 0.4ppm Predicted Linearity Error 10k - 5V KVD LTC1152 0.1F LT1010 OUTPUT + FLOATING, BATTERY-POWERED V NULL DETECTOR AN86 FC05 HP-419A Figure C5. Determining Buffer Error By Measuring Input-Output Deviation with Floating Microvolt Null Detector. Technique Permits Evaluation of Fixed and Operating Point Induced Errors The buffer is tested with Figure C5's circuit. As the KVD is run through its entire range, the floating null detector must remain well within 1ppm (5V), preferably below 0.5ppm. This test ensures that all error sources, particularly IB and CMRR, whose effects vary with operating point, are accounted for. Measured performance indicates the sum of all errors called out in Figure C4 is well within desired limits. In Figure C6, we add offset trim, a stable voltage source and a second KVD to drive the main KVD. Additionally, an ensemble of three HP3458A voltmeters monitor the output. The offset trim bleeds a small current into the main KVD ground return, producing a few microvolts of offset-trim range. This functionally trims out all sources of zero error (amplifier offsets, parasitic thermocouple mismatches and the like), permitting a true zero volt output when the main KVD is set to all zeros. The voltmeters, specified for < 0.1ppm nonlinearity on the 10V range, "vote" on the source's output. Circuitry Details Figure C7 is a more detailed schematic. It is similar to Figure C6 but highlights issues and concerns. The grounding scheme is single point, preventing mixing of return currents and the attendant errors. The shielded cables used for interconnections between the KVDs and voltmeters should be specified for low thermal activity. Keithley type SC-93 and Guildline #SCW are suitable. Crush type copper lugs (as opposed to soldered types) provide lower parasitic thermocouple activity at KVD and DVM connection points. However, they must be kept clean to prevent oxidation, thus avoiding excessive thermal voltages.2 A copper deoxidant (Caig Labs "Deoxit" D100L) is quite effective for maintaining such cleanliness. Low thermal lugs and jacks, preterminated to cables, are also available (Hewlett-Packard 11053, 11174A) and convenient. Thermal baffles enclosing KVD and DVM connections tend Note 1: See Appendix J, "Cables, Connections, Solder, Layout, Component Choice, Terror and Arcana," for relevant tutorial. Note 2: See above Footnote. AN86-9 Application Note 86 to thermally equilibrate their associated banana jack terminals, minimizing residual parasitic thermocouple activity. Additionally, restrict the number of connections in the signal path. Necessary connections should be matched in number and material so that differential cancellation occurs. Complying with this guideline may necessitate deliberate introduction of solder-copper junctions (marked "X" on Figure C7) to obtain optimum differential cancellation.3 This is normally facilitated by simply breaking the appropriate wire or PC trace and soldering it. Ensure that the introduced thermocouples temperature track the junctions they are supposed to cancel. This is usually accomplished by locating all junctions within close physical proximity. The noise filtering capacitor at the main KVD is a low leakage type, with its metal case driven by the output buffer to guard out surface leakage. ADJUST FOR 5.000000V AT A STABLE VOLTAGE SOURCE (LTZ1000A BASED) When studying the approach used, it is essential to differentiate between linearity and absolute accuracy. This eliminates concerns with absolute standards, permitting certain freedoms in the measurement scheme. In particular, although single-point grounding was used, remote sensing was not. This is a deliberate choice, made to minimize the number of potential error-causing parasitic thermocouples in the signal path. Similarly, a ratiometric reference connection between the KVD LTZ1000A voltage source and the voltmeters was not utilized for the same reason. In theory, a ratiometric connection affords lower drift. In practice, the resultant introduced parasitic thermocouples obviate the desired advantage. Additionally, the aggregate stability of the LTZ1000A reference and the voltmeter references (also, incidentally, LTZ1000A based) is comfortably inside 0.1ppm for periods of 10 minutes.4 This is more than enough time for a 10-point linearity measurement. 10k 0.1F 10k - LT1010 LTC1150 KVD 0.1F A + - LTC1152 +V MAIN KVD LT1010 + OUTPUT 0.000000V TO 5.000000V 20k OFFSET TRIM RWIRE HP3458A -V HP3458A HP3458A AN86 FC06 Figure C6. Simplified Sub-ppm Linearity Voltage Source Note 3: See Appendix J, "Cables, Connections, Solder, Layout, Component Choice, Terror and Arcana," for further discussion. Note 4: The LTZ1000A reference is detailed in Appendix I, " Voltage References." AN86-10 Application Note 86 Construction C10's measurement regime). This is more than 3 times better than the desired 1ppm performance, promoting confidence in our measurements.5 Figures C8 and C9 are photographs of the voltage source and the reference-buffer box internal construction. The figure captions annotate some significant features. Acknowledgments Results The author is indebted to Lord Kelvin and to Warren Little of the C. S. Draper Laboratory (nee M. I. T. Instrumentation Laboratory) standards lab. Warren taught me, with great patience, the wonders of KVDs some thirty years ago and I am still trading on his efforts. This KVD-based, high linearity voltage source has been in use in our lab for nearly two years. During this period, the total linearity uncertainty defined by the source and its monitoring voltmeters has been just 0.3ppm (see Figure SEE APPENDIX F FOR CIRCUIT DETAILS OF LTZ1000A ADJUST FOR 5.000000V AT A STABLE VOLTAGE SOURCE (LTZ1000A BASED) 10k 0.1F 10k - 10k KVD LT1010 LTC1150 0.1F A + - +V OFFSET TRIM 2k MAIN KVD 10k LTC1152 LT1010 + OUTPUT 0.000000V TO 5.000000V 20k 2F CASE -V HP3458A RWIRE HP3458A = SOLDER-COPPER JUNCTION. PLACEMENT AND NUMBER AS REQUIRED 2F = POLYSTYRENE. COMPONENT RSCH. CORP. HP3458A USE LOW THERMAL, LOW TRIBOELECTRIC SHIELDED CABLE FOR KVD AND DVM CONNECTIONS. SEE TEXT HIGH QUALITY GROUND AN86 FC07 Figure C7. Complete Sub-ppm Linearity Voltage Source Note 5: The author, wholly unenthralled by web surfing, has spent many delightful hours "surfing the Kelvin." This activity consists of dialing various Kelvin-Varley divider settings and noting monitoring A-to-D agreement within 1ppm. This is astonishingly nerdy behavior, but thrills certain types. AN86-11 Application Note 86 AN86 FC08.tif Figure C8. The Sub-ppm Linearity Voltage Source. Box Upper Right Is LTZ1000A Based Reference and Buffers. Upper Left Is Offset Trim. Reference and Main Kelvin-Varley Dividers Are Photo Center--Upper and Center-Middle, Respectively. Three HP3458 DVMs (Photo Lower) Monitor Output. Computer (Left Foreground) Aids Linearity Calculations AN86-12 Application Note 86 AN86 FC09.tif Figure C9. Reference-Buffer Box Construction. LTZ1000A Reference Circuitry Is Photo Lower Left, Buffer Amplifiers Photo Center. Note Capacitor Case Bootstrap Connection (Photo Center--Right). Single Point Ground Mecca Appears Photo Upper Left. Power Supply (Photo Top) Mounts Outside Box, Minimizing Magnetic Field Disturbance 1. 2. 3. 4. VERIFY KVD LINEARITY BY INTERCOMPARISON AND INDEPENDENT CAL. LAB. TAKE WORST-CASE VOLTMETER ENSEMBLE DEVIATIONS OVER 0V TO 5V, EVERY 0.5V 100 RUNS (10 PER DAY, ONCE PER HOUR) INDICATED RESULT IS 0.3ppm NONLINEARITY AN86 FC10 Figure C10. Testing Regime for the High Linearity Voltage Source AN86-13 Application Note 86 APPENDIX D A PROCESSOR-BASED CODE COMPARATOR The code comparator enforces the loop by setting the slave DAC inputs to the code that equalizes the user input and the LTC2400 A-to-D output. This action is more fully described on page one of the text. Figure D1 is the code comparator's digital hardware. It is composed of three input data latches and a PIC-16C5X processor. Inputs include user data (e.g., DAC inputs), linearity curvature correction (via DIP switches), convert command ("DA WR") and a selectable filter time constant. An output ("DAC RDY") indicates when the DAC output is settled to the user input value. Additional outputs and an DAC WR 4 5 6 7 1ppm 8 9 5V 11 2ppm The processor is driven by software code, authored by Florin Oprescu, which is described below. U2 74HCT574 2 3 5V input control and monitor the analog section (text Figure 2) to effect loop closure. Note that although a total of 32 bits are presented to the two 16-bit slave DACs, there are 8 bits of overlap, allowing a total dynamic range of 24 bits. This provides 4 bits of indexing range below the 20th bit, ensuring a stable LSB of 1ppm of scale. The 8-bit overlap assures the loop will always be able to capture the correct output value. 1 10 5V D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 19 18 17 16 15 14 13 12 CLK OE GND 20 20pF 0.1F 20pF VCC 4ppm LSB 4MHz CRYSTAL 5V FILTER U1 U3 74HCT574 2 3 4 5 6 USER DATA INPUT 7 8 9 11 1 10 D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 19 18 17 16 14 3 4 5 6 7 8 9 DAC RDY 11 1 10 4 5 10k 6 7 8 9 10 OE D0 3 12 20 VCC Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 11 12 13 14 USER INPUT PIC16C5X MCLR VDD CLKIN NC CLKIN2 VSS MSB D7 NC D6 ADC SCK D5 ADC SDO D4 NC D3 NC D2 LSB OE D1 MID OE LSB D0 MSB OE DAC RDY LSB WR DAC LD MSB WR MLBYTE 28 MCLR 27 26 5V 10k 25 10k 24 10k 23 10k 22 10k 21 10k 20 10k 19 10k 18 10k 17 16 10k 15 10k 10k 10k U4 74HCT574 2 0.1F 13 0.1F MSB 1 2 15 CLK GND 5V 19 10k 18 17 10k D7 MSB D6 D5 D4 D3 D2 D1 DAC COMMANDS TO ANALOG SECTION D0 DAC LD MLBYTE MSB WR LSB WR ADC SDO TO LTC2400 IN ANALOG SECTION ADC SCK 16 15 14 13 12 CLK OE GND VCC 20 0.1F AN86 FD01 Figure D1. Code Comparator Hardware. User Control Lines Are at Left, Analog Section Connections Appear at Right Side AN86-14 Application Note 86 ;20bit DAC code comparator ; ;*************************************************** ; * ; Filename: dac20.asm * ; Date 12/4/2000 * ; File Version: 1.1 * ; * ; Author: Florin Oprescu * ; Company: Linear Technology Corp. * ; * ; * ;*************************************************** ; ; Variables ;============ ; uses 17 bytes of RAM as follows: ; ; {UB2, UB1, UB0} user input word buffer ;------------------------------------------------------------------------------ ; 24 bits unsigned integer (3 bytes): ; ; The information is transferred from the external input register ; into {UB2, UB1, UB0} whenever a "user input update" event ; is detected by testing the timer0 content. Following the data ; transfer, the UIU ("user input update") flag is set and the DAC ; ready flags RDY and RDY2 are cleared. UB0 uses the same physical ; location as U0. The user input double buffering is necessary ; because the loop error corresponding to the current ADC reading ; must be calculated using the previous user input value. ; The old user input value can be replaced by the new user input ; value only after the loop error calculation. ; The worst case minimum response time to an UIU event must be ; calculated. The user shall not update the external input register ; at intervals shorter than this response time. For the moment the ; program can not block the user access to the external input ; register during a read operation. In such a situation the result ; of the read operation can be very wrong. ; ; UB0 - least significant byte. Same physical location as U0 ; ; UB1 - second byte. ; ; UB2 - most significant byte. ; ; ; {U2, U1, U0} user input word ;------------------------------------------------------------ ; 24 bits unsigned integer (3 bytes): ; ; The information is transferred from {UB2, UB1, UB0[7:4], [0000]} ; into {U2, U1, U0} whenever the UIU flag is found set within the ; CComp ("code comparator") procedure. The UIU flag is reset ; following the data transfer. AN86-15 Application Note 86 ; ; U0 - least significant byte of current DAC input ; The 4 least significant bits U0[3:0] are set ; to zero. ; ; U1 - second byte of current DAC input ; ; U2 - most significant byte of current DAC input ; ; ; {CON} control byte ;---------------------------------------- ; (1 byte): ; ; The 3 least significant bits CON[2:0] represent the ADC linearity ; correction factor transferred from UB[2:0] when the UIU flag ; is found set within the CComp procedure - at the same time as the ; {U2, U1, U0} variable is updated. ; ; The effect of CON[2:0] is additive and its weight is as follows: ; ; CON[0] = 1 linearity correction effect is about 1ppm ; CON[1] = 1 linearity correction effect is about 2ppm ; CON[2] = 1 linearity correction effect is about 4ppm ; ; The LTC2400 has a typical 4ppm INL error therefore the default ; curvature correction value can be set at CON[2:0] = 100 ; ; CON[3] is the control loop integration factor transferred from ; UB[3] when the UIU flag is found set within the CComp procedure. ; If CON[3]=0, after the control loop error becomes less than 4ppm ; the error correction gain is reduced from 1 to 1/4 ; If CON[3]=1, after the control loop error becomes less than 4ppm ; the error correction gain is reduced from 1 to 1/16 ; ; CON[7] is used as the UIU ("user input update") flag. It is set ; when {UB2, UB1, UB0} is updated and it is reset when {U2, U1, U0} ; and CON[3:0] are updated. ; ; CON[6] is used as the RDY ("DAC ready") flag. It is set when ; the DAC loop error becomes less than 4ppm and it is reset when ; the UIU flag is set. ; ; CON[5] is used as the RDY2 ("DAC ready twice") flag. It is set ; whenever the DAC loop error becomes less than 4ppm and the RDY ; flag has been previously set. It is reset when the UIU flag is set. ; ; ; The bit CON[4] is not used and is always set to 0. ; ; AN86-16 Application Note 86 ; {ADC3, ADC2, ADC1, ADC0} formatted ADC conversion result ;------------------------------------------------------------------------------------------------------------------ ; 32 bits signed integer (4 bytes). ; ; The ADC reading is necessary only for the calculation of the control ; loop error and in order to save RAM space, it can share the same ; physical space as the loop error variable. ; ; The LTC2400 output format is offset binary. It must be converted ; to 2's complement before any arithmetic operation. A number of ; possible codes are not valid LTC2400 output codes. If such codes ; are detected it can be inferred that a serial transfer error has ; occurred, the data must be discarded and a new conversion must ; be started. For all LTC2400 devices B31=0 and B30=0 always. In ; addition, with the exception of some early samples of the device ; the sequence B[29:28]=00 should not occur in a valid transaction. ; ; ADC0 - least significant byte ; contains ADC output bits B11(MSBIT) to B4 (LSBIT) ; ; ADC1 - second byte ; contains ADC output bits B19(MSBIT) to B12 (LSBIT) ; ; ADC2 - third byte ; contains ADC output bits B27(MSBIT) to B20 (LSBIT) ; ; ADC3 - most significant byte ; contains ADC output bits ~B29(as 7 MSBITS for ; 2's complement sign extension) and B28 (LSBIT) ; ; ; {ADCC} ADC curvature correction ;---------------------------------------------------------------- ; 8 bits unsigned integer (1 byte) ; ; The LTC2400 transfer characteristic has a typical INL of about ; 4ppm and a parabolic shape symmetric with respect to mid-scale. ; This error can be corrected to a first and second order and ; ADDC contains the magnitude of this correction. ; ; ; {ER3, ER2, ER1, ER0} control loop error value ;-------------------------------------------------------------------------------------------- ; signed integer (4 bytes) ; ; Contains the value of the current control loop error calculated ; as the difference between the previous user input and the last ; ADC reading. It is used to adjust the Low_DAC setting. Uses the ; same physical location as {ADC3, ADC2, ADC1, ADC0}: ; ; ER0 least significant byte, same location as ADC0 ; ; ER1 second byte, same location as ADC1 AN86-17 Application Note 86 ; ; ER2 third byte, same location as ADC2 ; ; ER3 most significant byte, same location as ADC3 ; ; ; {DL3, DL2, DL1, DL0} Low DAC control value ;-------------------------------------------------------------------------------------- ; signed integer (4 bytes): ; ; Contains the Low_DAC setting in a 2's complement, 32 bit ; format. Must be initialized to 0! ; ; DL0 least significant byte - used for Low_DAC ; control ; ; DL1 second byte - used for Low_DAC control after ; conversion to offset binary format {DL1, DL0} ; ; DL2 third byte - may be only 00 or FF ; ; DL3 most significant byte - may be only 00 or FF ; ; ; {INDX} Index variable for various program functions ;-------------------------------------------------------------------------------------------------------- ; 1 byte. ; ; ; {TMPV} Temporary variable for various program functions ;---------------------------------------------------------------------------------------------------------------- ; 1 byte. ; ; ; ; Algorithm ;=========== ; ; After each ADC conversion cycle the processor calculates the control ; loop error value as the difference between the desired output and ; the latest conversion result. Than it updates the DACs command ; such as to reduce the error magnitude. A new ADC conversion cycle ; is started following the DACs update operation. ; ; In order to maintain adequate control loop stability it is necessary ; for the DACs and the associated amplifiers to settle to better than ; 20 bits accuracy before the ADC starts sampling the system output. For ; an LTC2400 based system this settling time is 66ms. ; ; Initialization: ; Initializes the PIC controller and the hardware interface ; and starts the Scan procedure. ; AN86-18 Application Note 86 ; 1. Load ADC control port with default values ; SCKAD = 0 ; SDOAD = 1 ; 2. Set ADC control port I and O pins ; SCKAD = output ; SDOAD = input ; 3. Load register control port with default values ; NCSR[2:0] = 111 ; NCSD[1:0] = 11 ; ADDAC = 1 ; NLDAC = 1 ; DACRDY = 0 ; 4. Set register control port in output mode ; 5. Set data bus to default value DBUS[7:0]=0x00 ; 6. Set data bus in output mode ; 7. Initialize internal registers and variables: ; OPTION = 0x2F ; Timer0 used as counter is incremented by low-to-high edge ; Prescaler works with watch dog timer in div128 mode ; CON = 0x80 ; Simulate a UIU "user interface update" event to force ; the update of both Low_DAC and High_DAC ; {DL3, DL2, DL1, DL0} = 0 ; { U2, U1, U0} = 0 ; 8. Update hardware using the initialized variables ; 9. Start new ADC conversion by reading and discarding ; 32 serial bits. ; 10.Start the Scan procedure ; ; Scan: ; Continuously looks for "user input update" events. When ; a "user input update" event is detected updates the ; input buffer {UB2, UB1, UB0}, resets timer, sets UIU flag ; and resets RDY and RDY2 flags. ; ; The active low write signal for the external input register ; (which is the same as the user interface NWR input signal) ; is driven by the user and it is connected to the counter ; input of Timer0. The Timer0 is used in counter mode without a ; prescaler and it increments whenever a low-to-high transition ; is detected at its input. This is the same transition which ; latches in the input register a new user command. ; Because of the PIC controller timing constraints, this write ; signal must be maintained low for at least 2*Tosc + 20ns ; where Tosc is the maximum PIC clock period. When a 4 MHz ; clock is used for the PIC processor, the low time must be ; longer than about 520ns. ; ; 1. Test for "user input update" events by testing the Timer0 ; value. ; If Timer0>0 an UIU event has occurred. Reset the timer ; and answer Yes. ; If Timer0=0 answer No. AN86-19 Application Note 86 ; 1.1 If Yes, read input latch into {UB2, UB1, UB0}, ; reset DACRDY output line, set UIU flag and ; and reset RDY and RDY2 flags (CON[7:5]=100) ; Than continue ; 1.2 If No continue ; ; Continuously looks for the ADC end of conversion event. When ; the "end of conversion" is detected it reads the 28 most ; significant bits from the ADC and it constructs the ADC ; result {ADC3, ADC2, ADC1, ADC0} in 2's complement format ; If ADC3[1] == 0 => ADC3[7:1]=1111 111 ; If ADC3[1] == 1 => ADC3[7:1]=0000 000 ; For very early LTC2400 samples only, it is possible ; to obtain as a valid 0 conversion result ADC3[1:0]=00 ; In this case: ; If ADC3[1:0] == 0 => ADC3=0 ; It also calculates the first (x1) and second (x2) order ADC ; curvature correction ADCC as follows: ; x1 = {0x00, 0x80} ; -abs({ADC3, ADC2, ADC1, ADC0}/(2^16)-{0x00, 0x80}) ; x2 = {0x00, 0x40} ; -abs({0x00,{0,ADC2[6:0]},ADC1,ADC0}/(2^16)-{0x00,0x40}) ; ADCC = floor((x1 + x2/2) * {00000 CON[2:0]} / 4 ) ; The actual implementation uses only the least significant ; byte of x without any substantial additional error. ; Thus the above relation can be modified as follows: ; ADCC = floor((abs(ADC2) + abs({ADC2[6],ADC2[6:0]})/2) * ; * {00000 CON[2:0]} / 4 ) ; The maximum correction range is about 7ppm INL at mid ; scale for CON[2:0] = 111. ; ; 2. Test for ADC "end of conversion" event by testing the ; value of the ADC_SDO signal. ; If ADC_SDO = LOW answer Yes. ; If ADC_SDO = HIGH answer No. ; 2.1 If Yes read 28 most significant bits from the ADC, ; update {ADC3, ADC2, ADC1, ADC0} and calculate the ; curvature correction byte ADCC. Than start the CComp ; procedure. ; It should be noticed that while reading the first 28 ; most significant bits from the ADC the controller ; generates 27 serial clock pulses. An additional 5 serial ; clock pulses (for a total of 32) are necessary to restart ; the conversion. ; 2.2 If No restart the Scan procedure. ; ; ; CComp: ; Calculates the current control loop error as: ; ; error = current_user_input - ADC_reading + ; + new_user_input_LSB - current_user_input_LSB ; AN86-20 Application Note 86 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; The curvature correction is included in the ADC conversion result and is always positive therefore: ADC_reading = {ADC3, ADC2, ADC1, ADC0} + + { 0, 0, 0, ADCC} The term "new_user_input_LSB - current_user_input_LSB" represents the residue of the new user command which is added to the Low_DAC. {ER3, ER2, ER1, ER0} = = {0, U2, U1, U0} - {ADC3, ADC2, ADC1, ADC0} - { 0, 0, 0, ADCC} + + {0, 0, 0, UB0} - { 0, 0, 0, U0} = = {0, U2, U1, UB0} - {ADC3, ADC2, ADC1, ADC0} - { 0, 0, 0, ADCC}. The loop error {ER3, ER2, ER1, ER0} is a 32 bit signed number and the weight of the least significant bit is 1/16ppm of the ADC reference voltage. A 4ppm error value is represented as {0, 0, 0, 0x40}. The ADC output noise is dominated by thermal noise and has a white distribution. The control loop noise can be reduced by the square root of N by averaging N successive ADC readings. The obvious penalty is a slow settling time. Due to the limited amount of RAM available a direct implementation of this noise reduction strategy is difficult. In an equivalent implementation, when the absolute value of the loop error {ER3, ER2, ER1, ER0} decreases below a certain threshold, the gain of the error correction loop can be decreased. The default threshold is set at a very conservative 4ppm. This value must always be larger than the peak noise level of the ADC. A very quiet implementation can probably operate with a threshold of 2ppm. If CON[3]=0 the gain of the error correction loop is decreased from 1 to 1/4. If CON[3]=1 the gain of the error correction loop is decreased from 1 to 1/16. The High_DAC is always controlled by the 16 most significant bits of the most recent user command {UB2, UB1} The Low_DAC is controlled by the {DL3, DL2, DL1, DL0} variable which integrates the control loop error. Under correct operating condition abs({DL3, DL2, DL1, DL0})<2^15. In order to avoid roll-overs during large transients the {DL3, DL2, DL1, DL0} must be clamped within the +/- 2^15 range. The 16 bit Low_DAC can than be controlled by {DL1, DL0} after conversion to offset binary format. AN86-21 Application Note 86 ; The DACRDY output line reflects the state of the ; internal RDY2 flag. ; ; After the updates are completed we must start a new ADC ; conversion by completing the serial transfer. ; ; 1. Test if UIU flag is set ; 1.1 If Yes, move UB[3:0] into CON[3:0] ; and {UB0[7:4], 0000} into U0. The last ADC result ; is curvature corrected using the previous CON[3:0] value!. ; 2. Calculate {ER3, ER2, ER1, ER0}. ; 3. Test if UIU flag is set ; 3.1 If Yes, move {UB2, UB1} into {U2, U1} and ; clear UIU, RDY and RDY2 flags (CON[7:5]=000 ) ; 3.2 If No, test if abs({ER3, ER2, ER1, ER0}) < 4ppm ; 3.2.1 If Yes, test if CON[6]=1 (RDY flag) ; 3.2.1.1 If Yes, set RDY2 flag (CON[5]=1 ) ; 3.2.1.2 If No, set RDY flag (CON[6]=1 ) ; and test if CON[3]=0 (filter flag) ; 3.2.1.3 If Yes, {ER3, ER2, ER1, ER0} = ; = {ER3, ER2, ER1, ER0}/4 ; 3.2.1.4 If No, {ER3, ER2, ER1, ER0} = ; = {ER3, ER2, ER1, ER0}/16 ; 3.2.2 If No, clear UIU, RDY and RDY2 ; flags (CON[7:5]=000 ) ; 4 {DL3, DL2, DL1, DL0} = {DL3, DL2, DL1, DL0} + ; +{ER3, ER2, ER1, ER0}. ; 5. Update High_DAC, Low_DAC and DACRDY output line ; 6. Read the 4 least significant bits from ADC and start ; a new conversion ; 7. Restart the Scan procedure ; ; ; Hardware resources ;==================== ; ; Uses 8 input/output pins, 9 output pins, 1 input pin and 1 ; counter input pin ; ; DBUS[7:0] data bus ;-------------------------------------- ; 8 bit bi-directional data bus is used to read the 20 bit input ; command IC[19:0], the one bit filter selection FS[0] and the 3 bit ; curvature correction selection CC[2:0]. It is also used to write ; the 16 bit Low_DAC command LDAC[15:0] and the 16 bit High_DAC ; command HDAC[15:0]. ; ; assigned to PIC port C[7:0] ; AN86-22 Application Note 86 ; The data format for the read and write operations is as follows: ; ; DBUS[ 7:0] = IC[19:12] when NCSR[2] = 0 ; DBUS[ 7:0] = IC[11: 4] when NCSR[1] = 0 ; DBUS[ 7:0] = {IC[3:0], FS[0], CC[2:0]} when NCSR[0] = 0 ; LDAC[ 7:0] = DBUS[7:0] when NCSD[0] = 0 and ADDAC = 0 ; LDAC[15:8] = DBUS[7:0] when NCSD[0] = 0 and ADDAC = 1 ; HDAC[ 7:0] = DBUS[7:0] when NCSD[1] = 0 and ADDAC = 0 ; HDAC[15:7] = DBUS[7:0] when NCSD[1] = 0 and ADDAC = 1 ; ; ; NCSR[2:0] active low output enable controls for input registers ;-------------------------------------------------------------------------------------------------------------------------------- ; 3 output lines used to selectively enable the three 8-bit input ; registers in order to read the user updated DAC command, the 3 ; curvature correction bits and the one filter control bit. ; ; NCSR[0] enables the low input byte (LSB) and is assigned to port B[0] ; ; NCSR[1] enables the second input byte and is assigned to port B[1] ; ; NCSR[2] enables the high input byte (MSB) and is assigned to port B[2] ; ; ; NCSD[1:0] active low input enable controls for the DACs ;---------------------------------------------------------------------------------------------------------------- ; 2 output lines used to selectively enable the two DACs ; ; NCSD[0] enables the Low_DAC and is assigned to port B[3] ; ; NCSD[1] enables the High_DAC and is assigned to port B[4] ; ; ; ADDAC DAC address control ;---------------------------------------------------- ; output line. A low enables a write operation to the low byte of ; Low_DAC or High_DAC. A high enables a write operation to the high ; byte of Low_DAC or High_DAC. ; ; ADDAC is assigned to port B[5] ; ; AN86-23 Application Note 86 ; NLDAC active low DAC load control ;-------------------------------------------------------------------- ; output line. A high to low transition on this line updates the ; Low_DAC and High_DAC output values ; ; NLDAC is assigned to port B[6] ; ; ; DACRDY active high ready output signal ;------------------------------------------------------------------------------ ; output line. Indicates that the control loop error has been ; within a +/- 4ppm range for at least 250 ms ; ; DACRDY is assigned to port B[7] ; ; ; SCKAD external serial clock line for the ADC ;------------------------------------------------------------------------------------------ ; output line. ADC external serial clock. An external 10Kohm ; pull-down resistor is necessary on this line for correct ; power-up configuration. ; ; SCKAD is assigned to port A[0] ; ; ; SDOAD serial data line from ADC ;---------------------------------------------------------------- ; input line. Used to read ADC serial data. ; ; SDOAD is assigned to port A[1] ; ; ; ; NWRUI active low user interface write control ;-------------------------------------------------------------------------------------------- ; input line. The user must bring this line low in order to update ; the DAC input value. A minimum low and high time is required ! ; ; NWRUI is assigned to TOCKI counter input pin ; ; ; AN86-24 Application Note 86 ; The spare I/O pins A[3:2] are configured as outputs and maintained LOW. ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; list #include p=16c55A <p16c5x.inc> ; list directive to define processor ; processor specific variable definitions __CONFIG _CP_OFF & _WDT_ON & _XT_OSC ;VARIABLE DEFINITIONS ;==================== UB0 UB1 UB2 EQU EQU EQU H'0008' H'0009' H'000A' ; user input word buffer LSB ; user input word buffer second byte ; user input word buffer MSB U0 U1 U2 EQU EQU EQU H'0008' H'000B' H'000C' ; user input word LSB ; user input word second byte ; user input word MSB CON EQU H'000D' ; control byte ADC0 ADC1 ADC2 ADC3 EQU EQU EQU EQU H'000E' H'000F' H'0010' H'0011' ; ; ; ; ADCC EQU H'0012' ; ADC curvature correction byte ER0 ER1 ER2 ER3 EQU EQU EQU EQU H'000E' H'000F' H'0010' H'0011' ; ; ; ; control control control control loop loop loop loop DL0 DL1 DL2 DL3 EQU EQU EQU EQU H'0013' H'0014' H'0015' H'0016' ; ; ; ; Low_DAC Low_DAC Low_DAC Low_DAC LSB second byte third byte MSB INDX EQU H'0017' ; index variable TMPV EQU H'0018' ; temporary variable 0x2F 0x80 ; OPTION register default value ; CON register default value #define OPRDF #define CONDF ADC ADC ADC ADC conversion conversion conversion conversion result result result result error error error error LSB second byte third byte MSB LSB second byte third byte MSB AN86-25 Application Note 86 ;HARDWARE ASSIGNMENT DEFINITIONS ;=============================== #define DBUS PORTC ; 8bit I/O data bus #define #define #define #define #define REGCN REGDF NCSR0 NCSR1 NCSR2 PORTB 0x7F PORTB,0 PORTB,1 PORTB,2 ; ; ; ; ; register control port register control port default value LSB input register active low output enable second byte input register active low output enable MSB input register active low output enable #define #define #define #define NCSD0 NCSD1 ADDAC NLDAC PORTB,3 PORTB,4 PORTB,5 PORTB,6 ; ; ; ; Low_DAC active low write enable High_DAC active low write enable address bit for Low_DAC and High_DAC active low load control for Low_DAC and High_DAC #define DACRDY PORTB,7 ; 20bit_DAC ready indicator #define ADCCN #define ADCTR PORTA 0x02 #define ADCDF #define SCKAD #define SDOAD 0x02 PORTA,0 PORTA,1 ; ; ; ; ; ; ADC control port ADC control port configuration SDOAD input, the rest outputs ADC control port default value ADC external serial clock ADC serial data output ;THE CODE ;=============================== RESET start ORG goto 0x1FF start ORG 0x000 movlw movwf movlw tris ADCDF ADCCN ADCTR ADCCN movlw movwf clrw tris REGDF REGCN movwf tris DBUS DBUS REGCN movlw OPRDF option AN86-26 ; processor reset vector ;Initialization procedure ;------------------------------------------------ ;write ADC control port default value ; ;set the I and O pin states for the ;ADC control port ; ;write register control port default value ; ;set register control port pins as ;output only ; ;set DBUS default value of 0 ;set DBUS as output ; ;set OPTION register default value ; ; Application Note 86 clrf btfss movwf clrf clrf clrf clrf clrf clrf clrf movlw movwf movlw movwf goto fladc rddmy rduiu movlw movwf TMR0 ; STATUS,NOT_TO ;if this is not a power-on reset TMR0 ;load Timer0 with a nonzero value ;to force an initial read of the ;external input register ; DL3 ;initialize {DL3, DL2, DL1, DL0}=0 DL2 ; DL1 ; DL0 ; U2 ;initialize {U2, U1, U0}=0 U1 ; U0 ; ; CONDF ;set CON variable default value CON ; ;prepare to trigger a new ADC conversion ;after completing a hardware update 0x20 ;read and discard 32 serial bits from INDX ;the ADC ; iupdt ;go to the hardware update function 0x20 INDX bsf bcf decfsz goto btfss goto SCKAD SCKAD INDX,1 rddmy SDOAD fladc goto scan ;ADC output buffer flush function ;---------------------------------------------------------------- ;reads and discards 32 serial bits from ;the ADC ;ADC dummy serial read function ;------------------------------------------------------------ ;reads and discards the number of serial ;bits indicated by the INDX variable ;low-to-high ADC serial clock edge ;high-to-low ADC serial clock edge ;test if we read enough bits ;if No, read one more bit ;if Yes test that a new conversion has started ;if No, there is an interface problem. Flush the ;ADC output buffer and start a new conversion ;if Yes restart the scan procedure movlw tris bcf nop movf bsf DBUS,0 NCSR0 ;external input register read function ;-------------------------------------------------------------------------- ;input register read routine ;set data bus in read mode (input) ;output enable for input reg. LSB ;wait for data bus to settle ;read input reg. LSB ;output disable for input reg. LSB bcf movwf movf bsf NCSR1 UB0 DBUS,0 NCSR1 ;output enable for input reg. second byte ;store input reg. LSB into input buffer ;read input reg. second byte ;output disable for input reg. second byte 0xFF DBUS NCSR0 AN86-27 Application Note 86 scan bcf movwf movf movwf NCSR2 UB1 DBUS,0 UB2 ;output enable for input reg. MSB ;store input reg. second byte into input buffer ;read input reg. MSB ;store input reg. MSB into input buffer clrw bsf tris NCSR2 DBUS ;terminate input reg. read operation ;output disable for input reg. MSB ;return data bus to write mode clrf bcf TMR0 DACRDY ;clear Timer0 to continue wait for a UIU event ;signal user that input data has been read bsf bcf bcf CON,7 CON,6 CON,5 ;set UIU flag ;clear RDY flag ;clear RDY2 flag movf btfss goto TMR0,1 STATUS,Z rduiu btfsc goto SDOAD scan rdadc movlw movwf 0x1B INDX rdbit bsf bcf bcf btfsc bsf rlf rlf rlf rlf decfsz goto SCKAD SCKAD STATUS,C SDOAD STATUS,C ADC0,1 ADC1,1 ADC2,1 ADC3,1 INDX,1 rdbit AN86-28 ;scan procedure ;---------------------------- ;monitors UIU and end-of-conversion events ;test if Timer0 = 0 ;if Timer0=0 no UIU has occurred, skip next ;a user interface update has occurred ;go and read the new DAC input data ;test ADC end of conversion signal ;conversion not ready, rescan ;ADC serial read function ;------------------------------------------------ ;ADC conversion is done, read first 28 bits ;the first bit must be "0" to get here ;so do not bother with it ;low-to-high ADC serial clock edge ;high-to-low ADC serial clock edge ;move ADC output bit to carry. First clear carry ;read ADC output bit ;if ADC output is "1" set carry ;load carry as msb of ADC result ;and shift left all 4 bytes of the ADC result ; ; ;test if all 28 bits have been read ;if not, continue ; ;we have skipped the first ADC bit (ADC bit31=0) ;which has been tested as =0 when we detected the ;end of conversion. ;we have read 27 additional bits and have generated ;27 clock pulses. To restart the conversion we must ;produce the 5 remaining clock pulses Application Note 86 ; rdend btfsc goto ADC3,2 fladc ;verify validity of ADC serial data and format it ;------------------------------------------------------------------------------------------------ ;test if the ADC bit30 is "0" ;if not there is an interface problem. Flush the ;ADC output buffer and start a new conversion ;if yes, put the ADC result in 2's complement form movlw andwf 0x03 ADC3,1 ;first clear the 6 most significant bits in ADC3 ; btfsc STATUS,Z ;tests for the [ADC_B29,ADC_B28]=00 ADC output goto rdend ;if Yes the formatting is completed. ;in very early LTC2400 samples the ADC output code ;[ADC_B29,ADC_B28]=00 is valid goto fladc ;for current LTC2400 devices improved error ;detection capability is obtained if the ;previous line is replaced with this line. ;The replacement is not mandatory. ;For current LTC2400 parts the output code ;[ADC_B29,ADC_B28]=00 is not valid thus it may ;be assumed that an ADC interface error has ;occurred. Flush the ADC output buffer and start ;a new conversion movlw btfss movlw xorwf 0x02 ADC3,1 0xFE ADC3,1 ;if No, convert ADC3 in 2's complement form ; ; ; movf btfsc comf movwf ADC2,0 ADC2,7 ADC2,0 ADCC movf btfsc comf movwf rrf ADC2,0 ADC2,6 ADC2,0 TMPV TMPV,0 andlw addwf movwf 0x1f ADCC,0 TMPV clrf bcf btfsc ADCC STATUS,C CON,2 ;curvature correction calculator ;-------------------------------------------------------------- ;first order curvature correction multiplier ;use ADC2[7:0] as a 2's complement number ;calculate abs(ADC2) ;if ADC2[7]=0 w = ADC2 ;else w = !ADC2 ;ADCC=w=abs(ADC2) ;second order curvature correction multiplier ;use ADC2[6:0] as a 2's complement number ;calculate abs(ADC2[6:0]) ;if ADC2[6]=0 w = ADC2 ;else w = !ADC2 ;TMPV=w=abs(ADC2[6:0]) ;w=TMPV/2 in order to scale the second order ;curvature correction ;clear 3 MSB of w to complete calculation ;w=abs(ADC2)+abs(ADC2[6:0])/2 ;TMPV contains the curvature correction multiplier ; ; ;clear carry for div-by-2 operation ;if CON[2]=1 AN86-29 Application Note 86 movwf rrf movf bcf btfsc addwf rrf movf btfsc addwf ccomp ercalc ADCC TMPV,1 TMPV,0 STATUS,C CON,1 ADCC,1 TMPV,1 TMPV,0 CON,0 ADCC,1 ;ADCC=ADCC+abs(ADC2) ;TMPV=TMPV/2 ; ;clear carry for div-by-2 operation ;if CON[1]=1 ;ADCC=ADCC+abs(ADC2)/2 ;TMPV=TMPV/2 ; ;if CON[0]=1 ;ADCC=ADCC+abs(ADC2)/4 btfss goto movlw andwf movlw andwf iorwf CON,7 ercalc 0xF0 CON,1 0x0F UB0,0 CON,1 ;code comparator procedure ;-------------------------------------------------- ;if the UIU flag is clear ;skip CON[3:0] and U0 update ;else update CON[3:0] ;clear CON[3:0] ;extract new CON[3:0] ;from input buffer ;and load it movlw andwf 0xF0 UB0,1 comf comf movlw ADCC,1 ADC0,1 0x02 clrf addwf btfsc incf addwf btfsc incf addwf TMPV UB0,0 STATUS,C TMPV,1 ADCC,0 STATUS,C TMPV,1 ADC0,1 btfsc incf STATUS,C TMPV,1 AN86-30 ;move UB[7:4] to U0[7:4] ;UB0 and U0 use the same ;physical location ;calculate control loop error ;-------------------------------------------------------- ;ADCC 1's complement ;ADC0 1's complement ;add carry-in for ADCC and for ADC0 ;2's complement conversion ;prepare carry-out accumulator ;w=carry-in + UB0 ;if there is a carry-out ;accumulate it ;w=carry-in + UB0 - ADCC ;if there is a carry-out ;accumulate it ;ER0=UB0 - ADC0 - ADCC ;has same location as ADC0 ;if there is a carry-out ;accumulate it Application Note 86 comf movlw addwf clrf btfsc incf addwf btfsc incf addwf ADC1,1 0xff TMPV,0 TMPV STATUS,C TMPV,1 U1,0 STATUS,C TMPV,1 ADC1,1 btfsc incf STATUS,C TMPV,1 comf movlw addwf clrf btfsc incf addwf btfsc incf addwf ADC2,1 0xff TMPV,0 TMPV STATUS,C TMPV,1 U2,0 STATUS,C TMPV,1 ADC2,1 btfsc incf STATUS,C TMPV,1 comf decf ADC3,1 TMPV,1 movf addwf TMPV,0 ADC3,1 btfsc goto CON,7 lduiu ;ADC1 1's complement ;w=0xff (1's complement of ADCC second byte) ;w=0xff + carry-in ;prepare carry-out accumulator ;if there is a carry-out ;accumulate it ;w=0xff + carry-in + UB1 ;if there is a carry-out ;accumulate it ;ER1=U1 - ADC1 - 0 + carry-in ;has same location as ADC1 ;if there is a carry-out ;accumulate it ;ADC2 1's complement ;w=0xff (1's complement of ADCC third byte) ;w=0xff + carry-in ;prepare carry-out accumulator ;if there is a carry-out ;accumulate it ;w=0xff + carry-in + UB2 ;if there is a carry-out ;accumulate it ;ER2=U2 - ADC2 - 0 + carry-in ;has same location as ADC2 ;if there is a carry-out ;accumulate it ;ADC3 1's complement ;ADCC 2's complement term. The next ;carry-in is not useful - discard ;w=carry-in ;ER3= 0 - ADC3 - 0 + carry-in ;has same location as ADC3 ;test if the UIU flag is set ;go to U1, U2 update AN86-31 Application Note 86 movf btfsc comf btfss goto ER3,0 ER3,7 ER3,0 STATUS,Z nrdy ;error comparator ;-------------------------------- ;calculate absolute value of loop error and ;compare loop error magnitude with the 4ppm ;threshold ;W = ER3 ;test if {ER3, ER2, ER1, ER0} < 0 ;if yes W = -ER3 ;test if W=0 ;if not absolute error >= 4ppm movf btfsc comf btfss goto ER2,0 ER3,7 ER2,0 STATUS,Z nrdy ;W = ER2 ;test if {ER3, ER2, ER1, ER0} < 0 ;if yes W = -ER2 ;test if W=0 ;if not absolute error >= 4ppm movf btfsc comf btfss goto ER1,0 ER3,7 ER1,0 STATUS,Z nrdy ;W = ER1 ;test if {ER3, ER2, ER1, ER0} < 0 ;if yes W = -ER1 ;test if W=0 ;if not absolute error >= 4ppm movf btfsc comf andlw btfss goto ER0,0 ER3,7 ER0,0 0xC0 STATUS,Z nrdy ;W = ER0 ;test if {ER3, ER2, ER1, ER0} < 0 ;if yes W = -ER0 ;keep only W[7:6] which are bits >= 4ppm ;test if W[7:6]=0 ;if not absolute error >= 4ppm CON,6 CON,5 CON,6 ;if we are here the absolute loop error is ;less than 4 ppm. Set the flags and ;scale the loop error. ;test if RDY flag is already set ;if Yes, set RDY2 flag ;set RDY flag in any case btfsc bsf bsf AN86-32 Application Note 86 div4 lduiu nrdy eracc btfsc goto CON,3 div4 rrf rrf andlw btfsc iorlw movwf rrf rrf andlw btfsc iorlw movwf goto ER0,1 ER0,0 0x3F ER3,7 0xC0 ER0 ER0,1 ER0,0 0x3F ER3,7 0xC0 ER0 eracc ;error scaling ;-------------------------- ;reduce error correction value for loop ;damping and ADC noise reduction ;test if CON[3]=0 ;if Yes ER0=ER0/4 ;if No ER0=ER0/16 ;*1/2 ;*1/2 ;clear 2 most significant bits ;if {ER3, ER2, ER1, ER0} < 0 ;set 2 most significant bits ;ER0=ER0/4 ;*1/2 ;*1/2 ;clear 2 most significant bits ;if {ER3, ER2, ER1, ER0} < 0 ;set 2 most significant bits ;ER0=ER0/4 ;go to error accumulator UB1,0 U1 UB2,0 U2 0x1F CON,1 ;load latest user input ;-------------------------------------------- ; ;U1=UB1 ; ;U2=UB2 ; ;clear UIU, RDY and RDY2 flags ER0,0 TMPV DL0,1 STATUS,C TMPV,1 TMPV,0 TMPV ER1,0 STATUS,C TMPV,1 DL1,1 STATUS,C TMPV,1 TMPV,0 TMPV ER2,0 ;error accumulator ;---------------------------------- ;adds the current loop error to the ;previous Low_DAC control value ;{DL3, DL2, DL1, DL0}={DL3, DL2, DL1, DL0}+ ; +{ER3, ER2, ER1, ER0} ;the carry-in is 0 ;clear carry-in accumulator ;DL0=DL0+ER0 ;if there is a carryout ;accumulate in carry-in ;load carry-in ;clear carry-in accumulator ;W=ER1+carry-in ;if there is a carryout ;accumulate in carry-in ;DL1=DL1+ER1 ;if there is a carryout ;accumulate in carry-in ;load carry-in ;clear carry-in accumulator ;W=ER2+carry-in movf movwf movf movwf movlw andwf movf clrf addwf btfsc incf movf clrf addwf btfsc incf addwf btfsc incf movf clrf addwf AN86-33 Application Note 86 btfsc incf addwf btfsc incf movf addwf addwf ovflow STATUS,C TMPV,1 DL2,1 STATUS,C TMPV,1 TMPV,0 ER3,0 DL3,1 ;if there is a carryout ;accumulate in carry-in ;DL2=DL2+ER2 ;if there is a carryout ;accumulate in carry-in ;load carry-in ;W=ER3+carry-in ;DL3=DL3+ER3 btfss goto STATUS,Z negpot movf btfss goto DL2,1 STATUS,Z ovflow btfsc goto goto DL1,7 ovflow updt ;Low_DAC control truncation ;---------------------------------------------------- ;limits the {DL3, DL2, DL1, DL0} range to ; abs({DL3, DL2, DL1, DL0}) < 2^15 by ;truncation ;test if DL3=0 ;if No, DL may be negative ;if Yes, DL is positive ;test for overflow (>= 2^15) ; ;test if DL2=0 ;if No, DL >= 2^15, must truncate ;if Yes continue testing for overflow ;test if DL1[7]=1 ;if No, DL >= 2^15, must truncate ;if Yes we are done with DL range control clrf clrf movlw movwf movwf bcf goto DL3 DL2 0xFF DL0 DL1 DL1,7 updt ;if we arrive here DL >= 2^15. Must ;truncate to DL=2^15-1 => DL3=DL2=0 ;and DL1=0xEF, DL0=0xFF ; ; ; ;done with overflow correction AN86-34 Application Note 86 udflow clrf bsf clrf movlw movwf movwf goto DL1 DL1,7 DL0 0xFF DL3 DL2 updt ;if we arrive here DL < -2^15. Must ;truncate to DL=-2^15-1 => DL3=DL2=0xFF ;and DL1=0x80, DL0=0 ; ; ; ;done with underflow correction negpot btfss goto incf btfss goto incf btfss goto DL3,7 ovflow DL3,0 STATUS,Z udflow DL2,0 STATUS,Z udflow btfss goto DL1,7 udflow ;DL may be negative. Test if DL3[7]=1 ;if No, DL > 2^15, must truncate ;if Yes, DL <0. ;test if DL3=FF ;if No, DL < -2^15, must truncate ;if Yes continue testing for underflow ;test if DL2=FF ;if No, DL < -2^15, must truncate ;if Yes continue testing for underflow ;test if DL1[7]=0 ;if No, DL < -2^15, must truncate ;if Yes we are done with DL range control updt movlw movwf 0x05 INDX ;Hardware update function ;------------------------------------------------ ;Low_DAC and High_DAC update ; ;This is the hardware update function ;entry point for normal operation. ; ;prepare to generate the last 5 ADC external ;serial clock pulses ;when going to restart the scan procedure ;at the end of the hardware update function ;This will trigger a new ADC conversion. ; ;This is the hardware update function ;entry point for initial operation. ;The INDX variable has been initialized ;before to 0x2F which will generate ;32 serial clock pulses to the ADC thus ;starting a new conversion ; AN86-35 Application Note 86 iupdt clrw tris bcf movf movwf bcf bsf movf movwf bcf bsf bsf movf movwf bcf bsf movlw xorwf movwf bcf bsf bcf bsf DBUS ADDAC U1,0 DBUS NCSD1 NCSD1 DL0,0 DBUS NCSD0 NCSD0 ADDAC U2,0 DBUS NCSD1 NCSD1 0x80 DL1,0 DBUS NCSD0 NCSD0 NLDAC NLDAC btfsc bsf btfss bcf CON,5 DACRDY CON,5 DACRDY clrwdt goto END AN86-36 rddmy ;set the data bus in write mode ; ;set DAC address for LSB ;load High_DAC LSB ; ;write to High_DAC ; ;load Low_DAC LSB ; ;write to Low_DAC ; ;set DAC address for MSB ;load High_DAC MSB ; ;write to High_DAC ; ;change DL1 to offset binary ;load Low_DAC MSB ; ;write to Low_DAC ; ;load Low_DAC and High_DAC ; ;DACRDY output update ;test if RDY2 flag is set ;if Yes, set DACRDY output ;if No ;and only if No, clear DACRDY output ; ;clear watch dog timer ; ;generate the necessary number ;of ADC serial clock pulses in order ;to start a new conversion ; directive `end of program' Application Note 86 APPENDIX E LINEARITY AND OUTPUT RANGE OPTIONS The LTC2400 used as the feedback A-to-D element in the DAC has a typical 2ppm residual nonlinearity. Figure E1's lower curve shows this, along with the first order correction necessary (upper curve) to get nonlinearity inside 1ppm (center curve). If true 1ppm performance is necessary, the software based correction described in Appendix D can be utilized. The software generates the desired "inverted bowl" correction characteristic. The correction may be set to complement the residual nonlinearity characteristics of any individual LTC2400 via DIP switches at the code comparator. The LTC2410 offers another approach to improved linearity. This LTC2400 variant has improved linearity but specifies a maximum 2.5V input range. Figure E2 divides the DAC output with a precision resistor ratio set, allowing LTC2410 use while maintaining the 5V full-scale output. The disadvantage of this approach is the ratio set's additional 0.1ppm/C and 5ppm/year error contribution.1 Figure E3 is similar, although the ratio set's new value permits a 10V full-scale output. 10 LINEARITY ERROR (ppm) 8 CORRECTION CHARACTERISITIC 6 4 2 IDEAL CORRECTED ERROR 0 -2 -4 INHERENT ERROR -6 -8 -10 0 8,338,608 OUTPUT CODE (DECIMAL) 16,777,215 AN86 FE01 Figure E1. LTC2400 A-to-D Inherent Residual Linearity Error (Lower), Correction Characteristic (Upper) and Resultant Corrected Linearity (Center). Correction Ensures <1ppm Nonlinearity FROM DAC OUTPUT AMPLIFIER 5k *10ppm RATIO SET VISHAY VHD-200 0.1ppm/C FROM DAC OUTPUT AMPLIFIER OUTPUT 0V TO 5V * 5k IN (2.5V MAX) OUTPUT 0V TO 10V 7.5k LTC2410 (PARTIAL) DIGITAL OUTPUT TO CODE COMPARATOR AN86 E02 Figure E2. Precision Resistor Ratio Set Divides DAC Output, Permitting Higher Inherent Linearity LTC2410 Utilization. Disadvantage Is 5ppm/Yr and 0.1ppm/C Additional Drift Terms *10ppm RATIO SET VISHAY VHD-200 0.1ppm/C * 2.5k IN (2.5V MAX) LTC2410 (PARTIAL) DIGITAL OUTPUT TO CODE COMPARATOR AN86 E03 Figure E3. Similar to Figure E5, Except 3:1 Ratio Set Permits 10V Output While Accomodating LTC2410's 2.5V Input Note 1: The strata is becoming rarified when "error contribution" is delineated in fractional parts-per-million and the yearly drift rate noted. AN86-37 Application Note 86 APPENDIX F OUTPUT STAGES Some applications may require outputs other than the text circuit's 0V to 5V range. The simplest variation is a bipolar output, shown in Figure F1. The circuit, a summing inverter, subtracts the DAC output from a reference to obtain a bipolar output. Resistor and reference values may be varied to obtain different output excursions. The LT1010 output buffer provides drive capability and the chopper stabilized amplifier maintains 0.05V/C stability. The resistors introduce a 0.3ppm/C error contribution1 Figure F2 yields voltage gain by dividing the DAC output prior to its application to the feedback A-to-D. In this case, the 1:1 divider ratio sets a 10V output, assuming an A-to-D reference of 5V. As in Figure F1, the resistors add a slight temperature error, about 0.1ppm/C for the ratio set specified.2 Figure F3 uses active devices for voltage outputs as high as 100V. The discrete high voltage stage is driven in closed-loop fashion by a chopper stabilized amplifier. Q1 and Q2 furnish voltage gain, and feed the Q3-Q4 emitter follower outputs. Q5 and Q6 set current limit at 25mA by diverting output drive when voltages across the 27 shunts become too high. The local 1M-50k feedback pairs set stage gain at 20, allowing LTC1152 drives to cause full 0V TO 5V FROM DAC OUTPUT AMPLIFIER 120V output swing. The local feedback reduces stage gain-bandwidth, making dynamic control easier. This stage is relatively simple to frequency compensate because only Q1 and Q2 contribute voltage gain. Additionally, the high voltage transistors have large junctions, resulting in low fts, and no special high frequency roll-off precautions are needed. Because the stage inverts, feedback is returned to the amplifier's positive input. Frequency compensation is achieved by rolling off the amplifier with the local 0.005F10k pair. Heating and voltage coefficient errors are minimized in the feedback term by using four individual resistors. Trimming involves selecting the indicated resistor for exactly 100.0000V output with the DAC at full scale. Figure F4 increases output current capability with a current gain stage inside the DAC output amplifier's feedback loop. This stage replaces the LT1010 150mA buffer shown in the text. The figure shows two options, differing in output capacity. It is worth noting that as output current rises, wiring resistance becomes a large potential error term. For example, at only 10mA output, 0.001 of wiring resistance introduces 10V drop--a 2ppm error. Because of this, heavy loads should be supplied via short, highly conductive paths and remote sensing employed. 10k* 10k* 20k* -5V REFERENCE FROM DAC OUTPUT AMPLIFIER - LTC1152 LT1010 OUTPUT -2.5V TO 2.5V + *= VISHAY TYPE VHP-100 MATCHED SET AN86 FF01 Figure F1. Precision Resistors and Chopper Stabilized Output Amplifier Allow Bipolar DAC Output. Trade-Off Is 0.3ppm/C Additional Resistor Based Error OUTPUT 0V TO 10V 5k *VISHAY VHD-200 RATIO SET 0.1ppm/C * 5k USE 7.5k-2.5k VALUES FOR LTC2410 AN86 F02 Figure F2. x2 Voltage Gain Obtained By Feedback Division at A-to-D. Slight Increase in Overall Temperature Coefficient Results Note 1: See Note 1 in Appendix E. Note 2: See above footnote. AN86-38 TO LTC2400/LTC2410 A-TO-D INPUT Application Note 86 125V 1F 510 10k 330 Q1 2N5415 15V 0.005F Q3 2N3440* 50k Q5 2N2222 1M - 1k 27 1N4148 RSELECT*** TYPICAL 19.994k** 6 OUTPUT LTC1152 + INPUT FROM DAC 1N4148 50k 27 Q6 2N2907 1M 1k - 15V Q3 2N5415* Q2 2N3440 *HEAT SINK **VISHAY VHP-100 RESISTOR 0.01% ***1% METAL FILM RESISTOR 510 1F 330 - 125V 100k** 100k** 100k** 100k** AN86 FF03 Figure F3. High Voltage Output Stage Delivers 100V at 25mA. Multiple Feedback Resistors Minimize Dissipation and Voltage Coefficient Effects FROM TEXT FIGURE 2 (PARTIAL) 2k 0.1F - FROM MSB AND LSB DACs - LT1001 0.1F (OPTIONAL-- FOR INCREASED LOAD STABILITY) CC + + LT1206: 250mA OUTPUT LT1210: 1.1A OUTPUT AN86 FF04 Figure F4. LT1206/LT1210 Output Stages Supply 250mA and 1.1A Loads, Respectively. Remote Sensing Is Usually Necessary to Compensate IR Drops AN86-39 Application Note 86 APPENDIX G MEASURING DAC SETTLING TIME Measuring the 20-bit DAC's output settling time is a challenging task. Although the time scale involved is relatively slow, the 5V LSB step size presents problems. The issue reduces to obtaining a great deal of gain without inducing overdrive in the monitoring oscilloscope. Such overdrive will corrupt the measurement, rendering displayed results meaningless. Layout and construction of this circuit requires care. Figure G2 shows construction details. A linear layout minimizes parasitic feedback paths, preventing oscillation. The DAC input step is fully shielded, preventing feedthrough to various sensitive points within the amplifier. Finally, the entire circuit is built into a shielded enclosure to minimize effects of stray RF and pick up. Figure G1 is a solution. The DAC output is resistively balanced against a precision variable reference supply, adjustable in 0.5V steps.1 The circuit's remainder constitutes a clamped, distributed gain of 2000 amplifier. Diode clamping, placed at each gain stage input, prevents saturation from occurring even with large DAC-reference supply imbalances. The distributed gain allows 10kHz bandwidth while maintaining clamping effectiveness. The monitoring oscilloscope, operating at 5mV or 10mV/DIV (5V to 10V at the DAC output), can readily discern 5V settling without incurring deleterious overdrive. The circuit is tested by applying a test step that settles much faster than the DAC. Figure G3 uses a mercury wetted reed relay based pulse generator to supply the step. The unit noted is commercially produced, although similar results are obtainable with standard mercury based reed relays. When the relay opens the circuit's output settles essentially instantaneously (Figure G4) relative to DAC speed and settling time amplifier bandwidth. 0V TO -5V IN 0.5V STEPS FROM BUFFERED KVD BIASED FROM -5V REFERENCE Figure G1's response is tested by grounding one of its inputs and driving the other with the pulse generator. Figure G5 shows settling to within 1ppm (5V) in 2ms. This is much faster than the DAC settles, lending confidence to text Figures 6 and 7 indicated results. 5pF 20k* 20k* FROM DAC OUTPUT 0V TO 5V 5pF + 5.1k LT1008 - 9k 5pF + 5.1k LT1008 - 9k 1k 20pF + 5.1k LT1008 - 9k 1k * VISHAY VHD-200 RATIO SET 10ppm MATCHING 909k 1N4148 10 + 5.1k OUTPUT LT1008 - 5.1k 1k 5.1k 1N5712 15V CONNECT OUTPUT DIRECTLY TO OSCILLOSCOPE. DO NOT USE CABLE -15V 10k ZERO TO SET ZERO, GROUND BOTH INPUTS AND ADJUST "ZERO" FOR VOUT = <1mV AN86 FG01 Figure G1. Clamped, Distributed Gain-of-2000 Amplifier Permits DAC Settling Time Measurement Without Saturation Effects Note 1: See Appendix C for details on such a supply. AN86-40 Application Note 86 AN86 FG02.tif Figure G2. Settling Time Amplifier Construction. Bandwidth Is Only 10kHz, Although Gain of 2000 Necessitates Layout Care to Avoid Parasitic Feedback Induced Oscillation. Input (Photo Lower Left) Is Fully Shielded, Preventing Radiative Feedthrough to Amplifier. Enclosure Shields Circuit from Stray RF and Pickup AN86-41 Application Note 86 TEKTRONIX 067-0608-00 +V 25ms Hg REED RELAY OUTPUT FROM PULSE GENERATOR PULSE IN 50 TO DAC INPUT OF 30ms SETTLE CIRCUIT (GROUND SETTLE CIRCUIT REFERENCE INPUT) 5V AN86 FG03 Figure G3. Reed Relay Based Pulser Supplies Clean Step to Test Settling Time Circuit AN86 FG03.tif Figure G4. Mercury Wetted Reed Relay Opens in 5 Nanoseconds, Settles Quickly to Zero. 500MHz Ring-Off Derives from Source-Termination Impedance Mismatch 10V/DIV HORIZ = 2ms/DIV AN86 FE03.tif Figure G5. Settling Time Circuit Responds to Test Step with 2ms Settling to 1ppm (5V) AN86-42 Application Note 86 APPENDIX H MICROVOLT LEVEL NOISE MEASUREMENT Verifying DAC output noise requires a quiet, high gain amplifier at the oscilloscope. Figure H1 shows one way to take the measurement. The input preamplifier, operating at a gain of 1000, supplies a high pass cutoff at 0.1Hz. It drives the oscilloscope via a 10Hz discrete low pass filter. The oscilloscope, set to 1mV/DIV, indicates 1V/DIV referred to the preamplifier input. Figure H2 indicates DAC output noise well below an LSB, about 0.9V. Equipment limitations set measurement noise floor at 0.2V. Figure H3 shows the noise measurement test setup. Note that the signal levels involved dictate a completely shielded, coaxial path from breadboard to oscilloscope. The monitoring oscilloscope should have exceptional trace clarity. In the latter regard high quality analog oscilloscopes are unmatched. The exceptionally small spot size of these instruments is well-suited to low level noise measurement.1 The digitizing uncertainties and raster scan limitations of DSOs impose display resolution penalties. Many DSO displays will not even register the fine structure of the noise waveform. 500nV/DIV Figure H4 lists some applicable high sensitivity amplifiers suitable for the noise measurement. Current generation oscilloscopes rarely have greater than 2mV/DIV sensitivity, although older instruments offer more capability. The figure lists representative preamplifiers and oscilloscope plug-ins suitable for noise measurement. These units feature wideband, low noise performance. It is particularly significant that many of these instruments are no longer produced. This is in keeping with current instrumentation trends, which emphasize digital signal acquisition as opposed to analog measurement capability. FROM DAC OUTPUT PREAMPLIFIER A = 1000 HIGH PASS CUTOFF = 0.1Hz 1.6k (10Hz) OSCILLOSCOPE 1mv/DIV = 1V/DIV + 10F AN86 FH01 Figure H1. Microvolt Noise Measurement Necessitates High Gain Preamplifier for Oscilloscope. Preamplifier and Discrete Filter Set 0.1Hz to 10Hz Measurement Bandpass 2s/DIV AN86 F04.tif Figure H2. Indicated DAC Output Noise in a 0.1Hz to 10Hz Bandpass Is Below 1V, About 0.2LSB. Equipment Limitations Set Measurement Noise Floor at 0.2V Note 1: In our work we have found Tektronix types 453, 453A, 454, 454A, 547 and 556 excellent choices. Their pristine trace presentation is ideal for discerning small signals of interest against a noise floor limited background. AN86-43 Application Note 86 AN86 FH03.tif Figure H3. Noise Measurement Test Setup Includes Shielded DAC Breadboard (Foreground), Preamplifier (Left) and Low Pass Filter Attached to Oscilloscope (Center). Measurement Path Is Fully Coaxial AN86-44 Application Note 86 INSTRUMENT TYPE MODEL NUMBER MAXIMUM BANDWIDTH SENSITIVITY/GAIN AVAILABILITY COMMENTS Differential Amplifier Tektronix 1A7/1A7A 500kHz/1MHz 10V/DIV Secondary Market Requires 500 Series Mainframe, Settable Bandstops Differential Amplifier Tektronix 7A22 1MHz 10V/DIV Secondary Market Requires 7000 Series Mainframe, Settable Bandstops Differential Amplifier Tektronix 5A22 1MHz 10V/DIV Secondary Market Requires 5000 Series Mainframe, Settable Bandstops Differential Amplifier Tektronix ADA-400A 1MHz 10V/DIV Current Production Standalone with Optional Power Supply, Settable Bandstops Differential Amplifier Tektronix AM-502 1MHz 100,000 Secondary Market Standalone with Optional Power Supply, Settable Bandstops Differential Amplifier Preamble 1822 10MHz Gain = 1000 Current Production Standalone, Settable Bandstops SR-560 1MHz Gain = 50000 Current Production Standalone, Settable Bandstops, Battery or Line Operation MANUFACTURER Differential Amplifier Stanford Research Systems Figure H4. Some Applicable High Sensitivity, Low Noise Amplifiers. Trade-Offs Include Compatibility, Sensitivity and Availability APPENDIX I VOLTAGE REFERENCES Figure I1 lists some voltage reference options for use with the DAC. The self-contained types are convenient and easily applied. The LM199A and the LTZ1000A require external circuitry but offer higher performance. All choices must be trimmed to establish absolute DAC accuracy. The LTZ1000A offers the highest stability and is discussed below. Figure I2 shows the LTZ1000A and its support circuitry. A1 senses LTZ1000A die temperature and accordingly controls the IC heater via the 2N3904. A2 controls reference current. The Zener reference is sensed via Kelvin connections, minimizing voltage drop effects. A single point ground eliminates return current mixing and the attendant errors that would be produced. TYPE VOLTAGE Figure I3 offers choices for reference buffering. All employ a chopper stabilized amplifier augmented with a buffer output stage. Buffer error is extremely low, as noted in Appendix C's discussion. I3a, a simple unity-gain stage, transmits the input to the output with low error and minimal reference loading. I3b takes moderate gain, allowing a 7V reference input to produce (in this case) 10V at the output. I3c offers two ways to get 5V from the nominal 7V input. A precision divider lightly loads the reference in one case; the 5V output is taken at the LT1010. Reference loading is avoided by placing the divider at the output (optional case shown) and driving the A-to-D reference input from the divider output, which is permissible. INITIAL ACCURACY TEMPERATURE DRIFT LONG-TERM STABILITY COMMENTS LTZ1000A 7.2V Minimum 7V Maximum 7.5V 0.05ppm/C 4ppm/Yr Typical Highest Stability Zener Available. Requires External Heater Control and Reference Buffer Circuitry LM199A 6.95V 2% 0.5ppm/C 10ppm/Yr Typical Self-Contained, Including Heater Control Circuitry. Zener Output Is Unbuffered LT1021 5V, 7V, 10V 0.05V (7V) 2ppm/C (7V) 20ppm/kHr Noncumulative Fully Self-Contained. Trimmable LT1027 5V 0.02% 2ppm/C 20ppm/kHr Noncumulative Fully Self-Contained. Trimmable LT1236 5V, 10V 0.05% 5ppm/C 20ppm/kHr Noncumulative Fully Self-Contained. Trimmable Figure I1. Reference Choices Compared for Output Voltage, Accuracy and Stability. Highest Stability Types Require External Circuitry AN86-45 Application Note 86 ZENER + SENSE V+ 15V R4 13k 3 R2 70k + 1k 1N4148 + A1 LT1013 2N3904 10k - 6 1M R1 THROUGH R5: VISHAY VHP-100 0.1% HEATER, UNLABELED AND ZENER = LTZ1000A R3 70k 8 TEMP SENSOR 7 4 A2 LT1013 5 - 7 0.1F ZENER - SENSE 1 R1 120 R5 1k 0.1F 0.022F ZENER - FORCE HEATER PIN NUMBERS APPEAR FOR INDIVIDUAL LTZ1000A ELEMENTS 1N4148 2 HEATER RETURN Figure I2. 7V Reference Includes A1 Heater Control Amplifier, A2 Zener Current Regulator and LTZ1000A Zener. Note Zener Kelvin Connections and Single Point Ground 10k - 0.1F LTC1150 TO ZENER SENSE LT1010 OUT = 7.2V NOMINAL + 5k** 12.9k** - 0.1F LTC1150 TO ZENER SENSE LT1010 OUT = 10V NOMINAL + 10k - TO ZENER SENSE 22k* 0.1F LTC1150 LT1010 OUT = 5V NOMINAL + 50k* 2.2k** OPTIONAL, DELETE INPUT DIVIDER. SEE TEXT OUT = 5V NOMINAL 5k** * VISHAY VHP-100 - 1% ** VISHAY VHD-200 RATIO SET - 0.1% Figure I3. Chopper Stabilized Reference Buffer Options Include Unity Gain (a), 10V (b) and 5V (c) Output. Trimming Is Required for Absolute Accuracy AN86-46 SINGLE POINT GROUND AN86 I03 AN86 FI02 Application Note 86 CABLES, CONNECTIONS, SOLDER, COMPONENT CHOICE, TERROR AND ARCANA Subtle parasitic effects can have pronounced and seemingly inexplicable effects on low level circuit performance. Perhaps the most prevalent detractor to microvolt level circuitry is unintended thermocouples. Considerable discussion for dealing with thermocouples appeared in Appendix C and should be considered preliminary to this section's material. In 1822, Thomas Seebeck, an Estonian physician, accidentally joined semicircular pieces of bismuth and copper (Figure J1) while studying thermal effects on galvanic arrangements. A nearby compass indicated a magnetic disturbance. Seebeck experimented repeatedly with different metal combinations at various temperatures, noting relative magnetic field strengths. Curiously, he did not believe that electric current was flowing and preferred to describe the effect as "thermomagnetism." He published his results in a paper, "Magnetische Polarisation der Metalle und Erze durch Temperatur-Differenz" (see References). In low drift circuits, unwanted thermocouples are probably the primary source of error. Connectors, switches, relay contacts, sockets, wire and even solder are all candidates for thermal EMF generation. It is relatively clear that connectors and sockets can form thermal junctions. However, it is not at all obvious that junctions of wire from different manufacturers can easily generate 200nV/C-- four times a precision amplifier's drift specification! Figure J2 shows a plot obtained for such a wire junction. Even solder can become an error term at low levels, creating a junction with copper or Kovar wires or PC traces (see Figure J3). Figure J4 lists thermocouple potentials for some common materials found in electronic assemblies. 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 MICROVOLTS REFERRED TO 25C APPENDIX J 25 JUNCTION 30 35 40 DEGREES CENTIGRADE 45 AN86 FJ02 N W BISMUTH Figure J2. Thermal EMF Generated by Two "Identical" Copper Wires Due to Oxidation and Impurities 100 JUNCTION SLOPE 1.5V/C BELOW 25C E S AN86 FJ01 COMPASS Figure J1. The Arrangement for Dr. Seebeck's Accidental Discovery of "Thermomagnetism" Subsequent investigation has shown the "Seebeck Effect" to be fundamentally electrical in nature, repeatable and quite useful. Thermocouples, by far the most common transducer, are Seebeck's descendants. Unfortunately, unintended and unwanted thermocouples are also Seebeck's progeny. THERMALLY PRODUCED VOLTAGE IN MICROVOLTS COPPER 50 64% Sn/36% Pb 0 60% Cd/40% Sn SLOPE 160nV/C BELOW 25C -50 -100 10 20 30 40 50 0 SOLDER-COPPER JUNCTION DIFFERENTIAL TERMPERATURE SOURCE: NEW ELECTRONICS 2/6/77AN86 FJ03 Figure J3. Solder-Copper Thermal EMFs. Cd/Sn Has Notably Lower Activity but Is Toxic, Not Available and Not Recommended AN86-47 Application Note 86 The unusually energetic response of Cu-CuO necessitated the treatment described in Appendix C (Figure C7 and associated text) for cleaning DVM and Kelvin-Varley divider connections. Readers finding this figure's information seemingly academic should be awakened by Figure J5. This chart lists thermoelectric potentials for commonly employed laboratory connectors. Thermocouple activity of some types is more than 20 times greater than others. Be careful! Minimizing thermal EMF induced errors is possible if judicious attention is given to circuit board layout. In general, it is good practice to limit the number of junctions in the signal path. Avoid connectors, sockets, switches and other potential error sources to the extent possible. In some cases this will not be possible. In these instances, attempt to balance the number and type of junctions in the signal path so that differential cancellation occurs. Doing this may involve deliberately creating and introducing junctions to offset unavoidable junctions. This can be a tricky procedure. Repeated deliberate temperature excursions may be necessary to determine the optimal number and placement of added junctions. Experimentation, tempered by a healthy reserve of patience and abundance of time, is required. This practice, borrowed from standards lab procedures, can be quite effective in reducing thermal MATERIALS EMF originated drifts. Figure J6 shows a simple example where a nominally unnecessary resistor is included to promote such thermal balancing. For remote signal sources connectors may be unavoidable. In these cases, choose a connector specified for relatively low thermal EMF activity and ensure a similarly balanced approach in routing signals through the connector along the circuit board and to circuitry. If some imbalance is unavoidable, deliberately introduce an intentional counterbalancing junction. In all cases maintain the differencing junctions in close physical proximity, which will keep them at the same temperature. Avoid drafts and temperature gradients, which can introduce thermal imbalances and cause problems. Figure J7 shows the LTC1150 set up in a test circuit to measure its temperature stability. The lead lengths of the resistors connected to the amplifier's inputs are identical. The thermal capacity each input sees is also balanced because of the symmetrical connection of the resistors and their identical size. Thus, thermal EMF induced shifts are equal in phase and amplitude and cancellation occurs. Very slight air currents can still affect even this arrangement. Figure J8 shows a strip chart of output noise with the circuit covered by a small styrofoam cup (HANDI-KUPTM Company Model H8-S) and with no cover in "still" air. This data illustrates why it is often prudent to enclose low level circuitry inside some form of thermal baffle. POTENTIAL (V/C) Cu-Cu < 0.2 Cu-Ag 0.3 Cu-Au 0.3 Cu-Cd/Sn 0.3 Cu-Pb/Sn 1 to 3 Cu-Kovar 40 Cu-Si 400 Cu-CuO 1000 Source: Low Level Measurements, Keithley Instruments, 1984 (see References) Figure J4. Thermoelectric Potentials for Various Materials Indicates Inadvisability of Mixing Materials in Signal Path. Cu-Cu Connections (Chart Top) Must Be Kept Clean or 5000:1 Degradation Occurs As They Oxidize (Chart Bottom) HANDI-KUP is a trademark of WinCup. AN86-48 Application Note 86 CONNECTION TYPE DESCRIPTION THERMOELECTRIC POTENTIAL (V/C) BNC-BNC Mate 0.4 BNC-Banana Adapter 0.35 BNC-BNC "Barrel" Adapter 0.4 Male/Female Banana Mate Sample #1 0.35 Male/Female Banana Mate Sample #2 1.1 Male/Female Banana Mate (Type Specified for Low Thermal Activity) Sample #3 0.07 Copper Lug-Copper Banana Binding Post 0.08 Copper Lug-Standard Banana Binding Post 0.5 Plated Lug-Copper Banana Binding Post 1.7 Figure J5. Measured Thermoelectric Potentials for Some Common Laboratory Connectors. Pronounced Difference Between "Banana" Samples Is Due to Manufacturer's Materials Choice. Note That Copper Lug/Copper Banana Post Has 20x Lower Activity Than Plated Lug/Copper Banana Post AN86-49 Application Note 86 Thermal EMFs are the most likely, but not the only, potential low level error source. Electrostatic and electromagnetic shielding may be required. Power supply transformer fields are notorious sources of errors often mistakenly attributed to amplifier DC drift and noise. A transformer's magnetic field impinging on a PC trace can easily generate microvolts across that conductor in accordance with well known magnetic theory. The circuit cannot distinguish between this spurious signal and the desired input. Attempts to eliminate the problem by rolling off circuit response may work, but often the filtered version of the undesired pickup masquerades as an unstable DC term. The most direct approach is to use shielded transformers but careful layout may be equally effective and less costly. A circuit that requires the transformer to be close by to achieve a good quality grounding scheme may be disturbed by the transformer's magnetic field. An RF choke connected across a scope probe can determine the presence and relative intensity of transformer fields, aiding layout experimentation. Another source of parasitic error is stray leakage current. Such leakage currents must be prevented from influencing circuit operation. The simplest way to do this is to connect leakage sensitive points via teflon standoffs. Because the points never contact the PC board, stray leakage currents do not affect them. Although this approach is effective, its implementation may not be acceptable in production. Guarding is another technique for minimizing board leakage effects. The guard is a PC trace completely encircling the leakage sensitive points. This trace is driven at a potential equal to that of the point, preventing leakage to the "guarded" point. On PC boards, the guard should enclose the node(s) to be protected. Guarding was used to eliminate the effects of capacitor surface leakage in Appendix C's Figure C7. DELIBERATE SPLICE MAY BE DESIRABLE TO BALANCE OTHER JUNCTIONS NOMINALLY UNNECESSARY RESISTOR USED TO THERMALLY BALANCE OTHER INPUT RESISTOR LEAD WIRE/SOLDER/COPPER TRACE JUNCTION + OUTPUT - RESISTOR LEAD, SOLDER, COPPER TRACE JUNCTION AN86 FJ06 Figure J6. Typical Thermal Layout Considerations Emphasize Minimizing and Differencing Parasitic Thermocouples. Thermal Mass at Amplifier Inputs Should Be Equal, Allowing Differenced Parasitic Thermocouple Outputs to Arrive Matched In Phase and Amplitude 50k - 100 LTC1150 + EOS x 1000 50k AN86 FJ06 Figure J7. Amplifier Drift Test Circuit. Thermal EMFs and Thermal Capacity at Each Input Must Be Similar for Cancellation to Occur AN86-50 Application Note 86 AN86 FJ08.tif Figure J8. Effect of Thermal Baffle on Low Frequency Amplifier Noise in "Still" Air. Amplifier Is Covered By Small Cup in Upper Trace, Uncovered in Lower Trace. Instability Worsens If Air Movement Increases AN86-51 Application Note 86 AN86-52 Linear Technology Corporation an86f LT/TP 0101 4K * PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 FAX: (408) 434-0507 www.linear-tech.com LINEAR TECHNOLOGY CORPORATION 2001